1. Field of the Invention
The present invention relates to a NAND flash memory using, for example, EEPROM, and in particular, to a semiconductor memory device that can store multivalued data in each memory cell.
2. Description of the Related Art
In a NAND flash memory, a plurality of memory cells arranged in a column direction are connected together in series to constitute NAND cells, which are connected to corresponding bit lines via select gates. The bit lines are connected to latch circuits that latch write data and read data. Proposed NAND flash memories include nonvolatile semiconductor memory devices that can store multivalued data.
Elements have recently been increasingly miniaturized to reduce the distance between the cells. This has made the adverse effect of the floating gate capacitance between the adjacent cells more serious. Specifically, the threshold voltage of a cell on which a write operation has already been performed may disadvantageously be varied by the threshold voltage of a cell on which a write operation is subsequently performed. In particular, a multivalued memory in which 2 bits or more are stored in each cell stores a plurality of data using a plurality of threshold voltages. This requires the distribution of the threshold voltage for each data to be controllably significantly narrowed. This in turn results in the significant adverse effects of the threshold voltage of the adjacent cell.
To solve this problem, the following operation is performed. Before storing data in a memory cell in which 1 bit data (first page) has been stored, 1 bit (first page) data is written to the adjacent memory cell up to a threshold voltage (V-level) lower than the original one. After writing the data to the adjacent memory cell, a write operation on a second page write is performed with the threshold voltage raised to the original value (up to a word line voltage “b” (V<=B)). However, the write operation on the second page makes it impossible to determine whether the threshold voltage of the first page data is equal to or lower than the original one. Thus, to enable this determination, a proposed write scheme prepares a flag memory cell (hereinafter referred to as a flag cell) for each page and performs a read operation according to the flag cell data (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-195280).
Data read from a memory cell is first held in a first latch circuit and then output to the outside of the chip via a second latch circuit. While the data is being output to the outside of the chip via the second latch circuit, a read operation of reading the next read data from the memory cell to the first latch circuit can be performed (this operation is hereinafter referred to as cache read).
However, to reduce the area of the chip, only the second latch circuit can be connected to a device outside the chip. This configuration also applies to the flag cells. Flag cell data is read together with the corresponding memory cell data. Thus, in a cache read operation, the flag cell data cannot be distinguished from the memory cell data. Consequently, after the output of the data to the outside is finished, the data must be transferred from the first latch circuit to the second latch circuit to make a determination for the flag cell data. This disadvantageously reduces the speed of the cache read operation. It has thus been desirable to provide a semiconductor memory device that enables an increase in cache read speed.